1. Field of the Invention
This invention relates generally to non-volatile memory devices such as erasable and electrically programmable read-only memory (EPROM) cells; electrically, erasable programmable read-only memory (EEPROM) cells; and Flash EEPROM cells useful in memory arrays and programmable logic devices. More particularly, it relates to a shallow trench isolation structure and a method for fabricating isolation regions between active regions of an EEPROM cell in a semiconductor substrate so as to maintain sufficient data retention.
2. Description of the Prior Art
In recent years, there has been a trend of making semiconductor integrated circuits which contain higher and higher numbers of active devices packed more densely on the same silicon substrate area to provide increased complex functions and high performance. The density is dependent upon the area required to separate or isolate the active devices on the same semiconductor substrate from each other. In view of this, there has arisen a high interest by I.C. designers of developing various techniques to isolate such devices on the integrated circuits so as to achieve higher densities.
One of the most important isolation techniques developed, which has been used very extensively heretofore, is referred to as LOCOS (isolation for local oxidation of silicon). This LOCOS technique involves the formation of oxide in the non-active or field areas of the semiconductor substrate between active regions so as to prevent the electrical interaction of adjacent active devices. However, as the active device geometries were reduced to sub-micron dimensions, the effectiveness of the LOCOS isolation technique was significantly degraded because of large encroachments into the active devices which prevents scalability. As a consequence, alternative isolation processes were needed to overcome this drawback of the LOCOS technique.
Therefore, a newer isolation approach was developed referred to as trench/refill isolation in which trenches are etched between adjacent active regions of the semiconductor substrate. Basically, the trench/refill technique is divided into three categories as follows: (1) shallow trenches having a depth of less than 1 .mu.m, (2) moderate, deep trenches having a depth of between 1 to 3 .mu.m, and (3) deep, narrow trenches having a depth greater than 3 .mu.m and a width of less than 2 .mu.m.
There has been reported in an article entitled "Corner-Rounded Shallow Trench Isolation Technology to Reduce the Stress-Induced Tunnel Oxide Leakage Current for Highly Reliable Flash Memories" and authored by H. Watanabe et al., IEDM 96, pp. 833-836, that using corner-rounded shallow trench isolation for flash memories could reduce the stress-induced leakage current of the tunnel oxide so as to improve data retention.
Nevertheless, there still exists a need for a shallow trench isolation structure and a method for fabricating isolation regions between active regions of a EEPROM cell in a semiconductor substrate so as to maintain sufficient data retention.